pj34063 dc to converter controller 1 - 8 2002 / 01 . re v . a he pj34063 series is a monlthic contro l circuit containing the primary functions required for dc to dc onverters. these devices consist of an internal duty cycle oscillator with an active current limit circuit, drive and a high current output switch. this series was specifically designed to be incorporated in step-up, step- down and voltage-inverting applications with a minimum number of external components. temperature compensated reference,comparator,controlled operation from 3 to 40v input low standby current current limiting output switch current to 1.5a precision 2% reference output - voltage adjustable frequency of operation from 100hz to 100kh t device operating temperature packagge pj34063cd dip-8 pj34063cs -20 +85 sop-8 dip -8 sop -8 features block diagram pin : 1. switch collector 2. switch emitter 3. timing capacitor 4. gnd 5. comparator inverting input 6. vcc 7. ip k sense 8. driver collecto r ordering information
pj34063 dc to converter controller 2 - 8 2002/01.rev.a characteristic symbol value unit power supply voltage v cc 40 vdc comparator input voltage range v ir -0.3 ~ +40 vdc switch collector voltage v c(sw) 40 vdc switch emitter voltage v e(sw) 40 vdc switch collector to emitter voltage v ce(sw) 40 vdc driver collector voltage v c(drive) 40 vdc drive collector current (note 1) i c(drive) 100 ma switch current isw 1.5 a operating junction temperature t j +150 operating ambient t e mperature range t a -20 to +85 storage temperature range tstg -65 to +150 (v cc = 5.0v. ta= tlow to thigh. unless otherwise specified) characteristic s y mbol test condition min typ max unit oscillator frequency fosc v pin5 =0v, c t =1.0nf , t a =25 24 33 42 khz charging current i chg v cc =5 to 40v, t a =25 24 35 42 a discharge current i dischg v cc =5 to 40v, t a =25 140 220 260 a discharge to charge current ratio i dischg/ i chg pin7 to v cc , t a =25 5.2 6.5 7.5 - current limit sense voltage v ipk(sense) i chg = i dischg, t a =25 250 300 350 mv output switch(note 2) saturation voltage , darlington connection v ce(sat) isw=1.0a, pins1,8 connected - 1.0 1.3 v saturation voltage , darlington connection v ce(sat) isw=1.0a, r pin8 =82 to vcc, forced ? 20 - 0.45 0.7 v dc current gain h fe isw=1.0a, v ce = 5.0v, t a =25 50 75 - - collector off- state current i c(off) v ce =40v - 40 100 a comparator threshold voltage v th t a =25 1.23 1.25 1.27 v threshold voltage line regulation regline v cc = 3 to 40v 1.4 5.0 mv input bias current i ib v in =0v -20 -400 na total device supply current i cc v cc =5 to 40v, c t =1.0nf, pin7=vcc ,v pin 5>vth pin 2 =gnd, remaining pins open - - 4.0 ma notes : 1.maximum package power dissipation limits must be observed. 2.low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temper ature as possible. absolute maximum ratings electrical characteristics
pj34063 dc to converter controller 3 - 8 2002/01.rev.a figure 1.output switch on-off time versus oscillator timing capacitor figure 3.emitter follower config uration output saturation voltage versus emi tter current figure 5.current limit sense voltage versus temperature figure 2.timing capacitor waveform figure 4.common emitter config uration output switch saturation voltage versus collector current figure 6.standby supply current versus supply voltage
pj34063 dc to converter controller 4 - 8 2002/01.rev.a figure 1.step-up converter figure 2.external current boost connections for ic peak greater than 1.5a 2a.external npn switch 2b.external npn saturated switch
pj34063 dc to converter controller 5 - 8 2002/01.rev.a figure 3.step-down converter figure 4.external current boost connections for ic peak greater than 1.5a 4a.external npn switch 4b.external npn switch
pj34063 dc to converter controller 6 - 8 2002/01.rev.a figure 5.voltage inverting converter figure 6.external current boost connections for ic peak greater than 1.5a 6a.external npn switch 6b.external npn saturated switch
pj34063 dc to converter controller 7 - 8 2002/01.rev.a t able : d esign f ormula calculation step-up step-down voltage-inverting ton t o ff vout+v f -vin(min) v cc (min)-vsat-vout v out +v f v cc (min)-vsat-vout vout +v f v cc + vsat (ton+toff) max min 1 f min 1 f min 1 f c t 4.010 -5 ton 4.010 -5 ton 4.010 -5 ton i pk ( switch ) 2iout(max) ? ? ? ? ? ? ? ? + 1 toff ton 2iout(max) 2iout(max) ? ? ? ? ? ? ? ? + 1 toff ton rsc 0.3/i pk (switch) 0.3/i pk (switch) 0.3/i pk (switch) l (min) (max) )( (min) ton switchipk vsatvin = ? ? ? ? ? ? ? ?? (max) )( (min) ton switchipk voutvsatvin = ? ? ? ? ? ? ? ?? ? (max) )( (min) ton switchipk vsatvin = ? ? ? ? ? ? ? ?? co ? ? ? ? ? ? ? ? )( 9 ppvripple ioutton ? ? ? ? ? ? ? ?+ )(8 ))(( ppvripple tofftonswitchipk ? ? ? ? ? ? ? ? )( 9 ppvripple ioutton terms and definitions ? vsat = saturation voltage of the output switch. ? v f = forward voltage drop of the rectifier. the following power supply characteristics must be chosen: ? v in = normal input voltage ? vout: desied output voltage, | vout | =1.25 (1+ 1 2 r r ) ? iout : desired output current. ? fmin : minimum desired output switching frequency at the selected values for v in and.io. ? vripple(p-p): desired peak-to-peak output ripple voltage. in practice, the calculated capaitor value will need to be increased due to its equivalent series resistance and board layout. the ripple voltage should be kept to a low value since it w ill directly affect the line and load regulation.
pj34063 dc to converter controller 8 - 8 2002/01.rev.a millimeters inches dim min max min max a 9.07 9.32 0.357 0.367 b 6.22 6.48 0.245 0.255 c 3.18 4.43 0.125 0.135 d 0.35 0.55 0.019 0.020 g 2.54bsc 0.10bsc j 0.29 0.31 0.011 0.012 k 3.25 3.35 0.128 0.132 l 7.75 8.00 0.305 0.315 m - 10 - 10 millimet e rs inches dim min max min max a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27bsc 0.05bsc k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
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